Memory devices of the aforementioned type are disclosed for example in “IEEE International Solid-State Circuits Conference, Digest of Technical Papers” pages 278 and 279, and also in U.S. Pat. No. 6,317,375, both documents being hereby incorporated by reference. The former document especially reveals that, in such a memory, at the crossover locations of word and bit lines that run perpendicular to one another in rows and columns, passive memory elements are provided between the lines. These memory elements may comprise for example polymers, chalcogenites or magnetoresistive materials.
In the case of memory devices having polymers as memory elements, the memory effect is based on polar conducting polymer molecules. In this case, data is stored as permanent polarization that is generated by application of electric fields. The resistance of the memory element depends on the polarization orientation of the polymer molecules.
In the case of memory devices having magnetoresistive (ferromagnetic) materials as memory elements, the resistance depends on the orientation and magnitude of the spin polarization of the ferromagnetic materials.
A large or small resistance results depending on the orientation and magnitude of the polarization in the materials mentioned above. These resistances may in each case be assigned a digital logic level. Thus, a large resistance may correspond to a logic “1” and a small resistance may correspond to a logic “0”.
FIG. 1 of the drawings shows a detail from a memory 10 having memory elements 12, which are illustrated at resistors for the sake of simplicity. These memory elements are situated at crossover locations of word lines . . . , WLk−1, WLk, WLk+1, . . . and bit lines . . . , BLi−1, BLi, BLi+1, . . . . These memory elements 12 shall be programmed in the sense described above, so that they have either a large resistance corresponding to a logic “1” or a comparatively small resistance corresponding to a logic “0”.
By way of example, the memory element 12 with a black backing in FIG. 1 is now intended to be read, the memory element being situated on the bit line BLi and the read line WLk. For this purpose, a measurement voltage UMeas of 1 V may be applied to the bit line BLi at a terminal 14 and a voltage of 0V may be applied to the read line WLk, while a voltage of 1 V is present on all the other word lines . . . , WLk−1, WLk+1, . . . . In the ideal case, a measurement current IMeas then flows only via the memory element 12 with a black backing, the measurement current being indicated on an ammeter 16. The value of this measurement current IMeas depends on the resistance of the memory element 12 and represents either a logic “1” equal to a large resistance or a logic “0” to a small resistance.
In practice, however, this ideal case is not afforded since a parasitic current also flows via all the other memory elements 12 situated on the bit line BLi if the voltage at the terminal 14 has a value that deviates from UMeas=1 V.
FIGS. 2A and 2B show a possible realization for reading out information by means of a differential amplifier 20 having relative feedback via a resistor RS, the negative input of the amplifier being connected to the terminal 14 of the bit line BLi and the measurement voltage UMeas being present at the negative input of said amplifier. Given the voltages specified in FIG. 1, however, a voltage Ux that differs from 0 is present, rather than the voltage 0, in the practical case. An output signal U0 of the differential amplifier 20 represents the read signal.
In accordance with FIG. 2B, an equivalent resistance RP shall be the resulting resistance of all the memory elements 12 that are not to be read on the bit line BLi. A parasitic current flows via said equivalent resistance RP, the value of said current depending on the logic state of all the memory elements 12 that are not to be read on the bit line BLi.
An explanation shall be given firstly of the state in which the memory element 12 to be read contains a logic “0”, which shall correspond to a resistance of, for example, 103 ohms. If all further memory elements 12 not to be read on the bit line BLi contained a logic “1”, then that would correspond to a resistance of e.g., 1 Mohm. Given 1000 cells that are not to be read on the bit line BLi, for example, then for this case the parasitic resistance RP would be equal to 1 Mohm/1000 which equals 1 kohm.
On the other hand, if all the memory elements 12 that are not to be read and are situated on the bit line BLi contained a logic “0” with a resistance of 103 ohms, then given 1000 memory elements 12 that are not to be read, the result would be a parasitic resistance RP of 103 ohms/1000 which equals 1 ohm.
Corresponding conditions result if the memory element 12 to be read contains a logic 1, limit values for the parasitic resistance RP of 1 kohm and 1 ohm likewise resulting.
The parasitic current flowing via the parasitic resistance RP thus fluctuates greatly in a manner dependent on the logic levels in the memory elements 12 that are not to be read on the bit line BLi, which leads to corresponding fluctuations in the voltage Ux at the input of the differential amplifier 20. The read signal U0 at the output of the differential amplifier 20 fluctuates correspondingly.
The diagram according to FIG. 3, illustrating the output voltage U0 of the differential amplifier 20 over time, shows a range 30 of output voltages U0 for a read-out “0” and a range 31 of output voltages U0 for a read-out “1”. An upper voltage value 30-1 of the voltage range 30 represents the case in which the memory element 12 that is read is surrounded by all logic levels “1”, while a lower voltage value 30-2 represents the case in which the memory element 12 that is read is surrounded by all logic levels “0”. Correspondingly, an upper value 31-1 of the voltage range 31 represents the case in which the memory element 12 that is read is surrounded by all logic levels 1, while a lower voltage value 31-2 represents the case in which the memory element 12 that is read is surrounded by all logic levels “0”. The respective intermediate voltage values of the voltage ranges 30 and 31 represent cases in which the memory element 12 that is read is surrounded both by logic levels “1” and by logic levels “0”.
A range 32 between the ranges 30 and 31 represents the signal-to-noise voltage ratio at the input of the differential amplifier 20.
A possible improvement in the situation explained above constitutes for example allocating a fixed voltage to non-selected bit and word lines. This results in an improved evaluation of the read signal, but two switches and thus additional layout space are required at each word and bit line.
A further possibility for the configuration of a memory is described “IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, as mentioned in the introduction. In this case, reading is effected in two steps, a first step determining the memory element current through the selected memory element as a result of the parasitic current and a second step determining a known current of a previously written “0” flowing via a reference cell plus the same parasitic current. The current determined in the second step is subtracted from the total current determined in the first step, so that only the current through the memory cell that is read is measured relative to the reference current. However, this requires, on each word and bit line, an additional decoder in the memory, with the result that the latter does not manage without active components.